By Ping-Sheng Tseng
Widespread use of parallel processing becomes a truth provided that the method of porting purposes to parallel pcs will be principally automatic. frequently it truly is undemanding for a consumer to figure out how an software will be mapped onto a parallel computing device; even though, the particular improvement of parallel code, if performed by means of hand, is sometimes tricky and time eating. Parallelizing compilers, that could gen erate parallel code instantly, are for that reason a key expertise for parallel processing. during this booklet, Ping-Sheng Tseng describes a parallelizing compiler for systolic arrays, referred to as AL. even supposing parallelizing compilers are very common for shared-memory parallel machines, the AL compiler is without doubt one of the first operating parallelizing compilers for dispensed reminiscence machines, of which systolic arrays are a unique case. The AL compiler takes good thing about the superb grain and excessive bandwidth interprocessor verbal exchange features in a systolic structure to generate effective parallel code. xii Foreword whereas in a position to dealing with an incredible category of functions, AL isn't really meant to be a general-purpose parallelizing compiler.
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Extra info for A Systolic Array Parallelizing Compiler
The loops represent the type of computation kernels typically found in large-scale scientific computing. Although the original Fortran programs do not declare DARRAYs, we simply determine which arrays have linear indexing patterns. Since 16 out Data relations 27 of the 24 loop kernels have linear indexing patterns, we can at least claim that linear data relations frequently occur in real life scientific computing applications. For a DO* loop with linearly related DARRAY slices, every iteration has its own data compatibility class, which is the union of all the DARRAY slices referenced in the iteration.
1 shows that just packing two data compatibility classes into a cell will avoid duplicating DARRAY slices in nonadjacent cells . -- ... .. C3 ..... ~i3j··.. :i l\,> '. ".. A[Sj .... 1: Blocking We call such a loop distribution scheme the blocking scheme. Formally, the blocking scheme assigns data compatibility class Ci to cell Loop Distribution Li/wJ 43 of the systolic array, where w is a parameter to be deter- mined by the compiler. The blocking scheme not only localizes the communication for updating distributed variables but also localizes the communication for updating normal variables because two consecutive loop iterations are either executed in the same cell, which requires no communication, or in two neighboring cells, which only requires local communication.
To formulate the data compatibility classes of DARRAYs X lJ X 2 , ••• ,Xm in a DO* loop, we have data compatibility class Ci for loop iteration i: U XIe[dle' i + q]. [dle . i + q] referenced in iteration i of the DO* loop, where lie is the minimum value of q and rle is maximum value of q. We use [lie, q, rle] to denote the upper and lower bounds of q, it does not mean all the integers between lie and 28 A Systolic Array Parallelizing Compiler ric. 1 have the property that: IT w ~wo then where wo=mur l~lc~m ric - llc d 1 Ic This property guarantees that there are no intersections among data compatibility classes whose indices are more than Wo away.
A Systolic Array Parallelizing Compiler by Ping-Sheng Tseng